Display technologies, such as liquid crystal display (LCDs), can activate segments of a display according to signals applied across the segments. Conventionally, technology for driving LCDs directly requires dedicated hardware to generate and sequence specific analog voltage levels in order to properly drive a display. Waveforms are generated using such multiple signal levels to either turn on or off each segment. Typically, such multiple signal levels include a high bias voltage, and multiple other intermediate voltage levels proportional to the high bias voltage. A high bias voltage is typically an analog value that may be varied to increase or decrease a contrast of display segments. The generation of a variable high bias voltage and multiple intermediate voltages can be costly in terms of integrated circuit die area, and in some cases power.
A typical LCD display may include multiple “commons”. Each common may be connected to a corresponding set of LCD segments. Commons may be driven to an analog selection voltage in a time division multiplexed fashion such that only one commons is driven to an analog selection voltage at a time. When not driven to a selection voltage, each common may be driven to one of many different analog de-selection voltage levels.
While LCDs segments may be activated by applying a voltage bias, in order to avoid damaging such segments, LCD controls signals must have an overall DC bias of zero.
For systems having N commons, voltages relative to the high bias value may include 1/(1+√N), 2/(1+√N). Further, to ensure a zero DC bias is maintained across each segment, additional values are needed that may be arrived at by “flipping” the previously voltage levels, which gives: √N/(1+√N) and (√N−1)/(1+√N).
As but one example, for a system having eight commons, the different analog voltage levels would be 0%, 28%, 56% and 100%. As noted above, to preserve a DC bias across a segment, you must complement (1−x %) these values, and thus include voltage levels 100%, 72%, 44% and 0%. Hardware to generate these levels can require the generation of the high bias voltage (100%), and the ability to generate the four levels proportional to this high bias level.
Such levels can be expressed in terms of a value α as follows:
            V      C        =                  N            *              V        S                                V        C            +              V        S              =          100      ⁢      %                          V        C            +              V        S              =                            100          ⁢          %                →                              V            S                    +                      α            *                          V              S                                          =                          ⁢                          ⁢                          ⁢                                    100            ⁢            %                    →                                    V              S                        *                          (                              1                +                α                            )                                      =                                            100              ⁢              %                        →                          V              S                                =                                    100              ⁢              %                                      1              +              α                                          
If resistor ladders are employed to voltage divide a high bias voltage, there may be overlap in the resistor ranges (α=1 and α=3) and some values can be reused, but for the most part, there may be little overlap, with each a setting needing its own set of resistors in the divider. Thus, for any system which plans to support many commons, a divider with many resistors must be constructed to generate the voltages. This also requires a complicated analog multiplexer to select the different voltage levels. Once the device is made, there may not exist a way to add more commons since the architecture is fixed.
One example of a conventional LCD driving arrangement is shown in FIGS. 16A and 16B. FIGS. 16A and 16B show an arrangement having three commons.
Referring to FIG. 16A a number of analog waveforms are shown, including a common waveform (COM0), two segment selection waveforms (SEG0, SEG1), and waveforms showing a resulting voltage difference between the common levels and segment selection levels (COM0-SEG0, COM0-SEG1). The waveforms show three timeslots t0, t1 and t2. Such three time slots may make up a frame.
As shown, common signal COM0 varies between a high analog bias voltage (Van_HI), and two values proportional to this voltage (Van_HI*(2/3), Van_HI*(1/3)), and a low voltage (GND). Signal COM0 is driven to a high selection level during timeslot t0.
Segment selection waveform SEG0 is driven with a selection state with respect to the signal COM0. Accordingly, as shown by the hatched portion of waveform COM0-SEG0, a voltage across a segment may exceed a threshold (Vth, −Vth), resulting in a segment being activated at timeslot t0. In timeslots t1 and t2, levels remain below Vth/−Vth, so the segment is not activated.
In contrast, segment selection waveform SEG1 is driven with de-selection state with respect to the signal COM0. Accordingly, as shown by waveform COM0-SEG0, a voltage across a segment never exceeds a threshold (Vth, −Vth), resulting in a segment remaining de-activated.
It is understood that FIGS. 16A and 16B show a very limited number of commons, and that LCD assemblies may include substantially larger numbers of commons (i.e., twenty or more), in which additional analog levels may be required.
Generating such selection and de-selection analog voltage levels can be quite expensive. As noted above, such analog circuits may be implemented with resistors, however such resistors must typically have tight tolerances. This can be costly in device area and/or require special process steps. Further, the analog circuitry require to generate multiple analog voltage levels may also be costly. Conventional analog control circuits for an LCD are shown in FIGS. 17A and 17B.
FIG. 17A shows a first portion of a conventional system 1700 that generates a high bias voltage v0 and four proportional intermediate voltages v1, v2, v3 and v4. System 1700 includes a band gap reference circuit 1702 that provides a temperature independent voltage Vbg to operational amplifier (op amp) 1704. Op amp 1704 may drive bias transistor P170. A drain of transistor P170 may be fed back to op amp 1704 by an adjustable feedback bias circuit that includes adjustment switches 1706, and resistances R1 and R2. In response to contrast input values CONTRAST, adjustment switches 1706 may vary resistance values R1/R2 to alter an op amp 1704 driving voltage to generate a desired high bias voltage v0 (where v0=(1+R1/R2*Vbg)).
A high bias voltage v0 may be provided to a resistance ladder network 1708 that may include high precision resistors for generating a large number of bias voltages to accommodate different display types, as well as varying numbers of commons. In response to bias select values (BIAS SELECT), a selection circuit 1710 may connect four generated analog output voltages from resistance ladder network 1708 as output voltage v1, v2, v3 and v4. It is understood that selection circuit 1710 is an analog circuit that must be capable of passing the various different analog voltage levels.
FIG. 17B shows a second portion of a conventional system 1700 that outputs one of many different analog voltages as a common signal or segment control signal. The various generated analog voltage v0, v1, v2, v3, v4 and GND may be selectively output from a first analog multiplexer (MUX) 1712 in response to common/segment (COM_SEG) selection values. Values output form first analog MUX 1712 may be selectively output to a buffer circuit 1716 from second analog MUX 1714 in response to display and frame data (DISP_DATA, FRAME). FIGS. 17A and 17B show how a conventional approach may require considerable analog circuit resources.
It is noted that to accommodate a wide range of LCD voltage levels, a high supply voltage (e.g., Vpwr_Hi in FIG. 17A) may be generated by a voltage digital-to-analog converter (VDAC), which may further add to the size and complexity of the system.
It is also noted that other conventional approaches may utilize charge pumps in lieu of resistance ladder networks to arrive at various analog bias voltages. Such an approach also consumes considerable die area and power.